作业帮Verilog 语法问题按键消抖程序的一部分reg [2:0] key_r;always@(posedge clk or negedge r_est)beginif(!r_est) key_r
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![Verilog 语法问题按键消抖程序的一部分reg [2:0] key_r;always@(posedge clk or negedge r_est)beginif(!r_est) key_r](/uploads/image/z/6801799-31-9.jpg?t=Verilog+%E8%AF%AD%E6%B3%95%E9%97%AE%E9%A2%98%E6%8C%89%E9%94%AE%E6%B6%88%E6%8A%96%E7%A8%8B%E5%BA%8F%E7%9A%84%E4%B8%80%E9%83%A8%E5%88%86reg+%5B2%3A0%5D+key_r%3Balways%40%28posedge+clk+or+negedge+r_est%29beginif%28%21r_est%29+key_r)
Verilog 语法问题按键消抖程序的一部分reg [2:0] key_r;always@(posedge clk or negedge r_est)beginif(!r_est) key_r
Verilog 语法问题
按键消抖程序的一部分
reg [2:0] key_r;
always@(posedge clk or negedge r_est)
begin
if(!r_est) key_r
Verilog 语法问题按键消抖程序的一部分reg [2:0] key_r;always@(posedge clk or negedge r_est)beginif(!r_est) key_r
你是不是错误提示：Error (10200):Verilog HDL Conditional Statement error at ……:cannot match operand(s) in the condition to the corresponding edges in the enclosing event control of the always construct
这是因为,你的“always@(posedge clk or negedge r_est)”表明在clk上升沿或r_est下降沿这两个敏感事件发生时always语句块得以触发；而always中的if条件语句必须至少有一个条件指向其中一个敏感事件（边界标识符）；所以写成“if（r_est)...else...”就会出错.
你可以把“always@(posedge clk or negedge r_est)”改为“always@(posedge clk or posedge r_est)”再编译试试,应该就没问题了.
你右键该错误点击“Help”里是这么说的：
CAUSE:In a conditional statement at the specified location in a Verilog Design File (.v),you specified a condition that Quartus II Integrated Synthesis cannot use to classify the edges in the enclosing always construct's event control.When an event control contains multiple edges,Quartus II Integrated Synthesis distinguishes the asynchronous control signals from the clock by analyzing the conditional statements in the always construct.For example,the following code fragment contains an always construct whose event control contains three edges---two asynchronous resets and a clock.
always @ (posedge clk or posedge rst1 or posedge rst2)
begin
if ( rst1 || rst2 )
q